1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. More specifically, it relates to a nonvolatile semiconductor memory, which employs a metallic salicide film as an electrode film.
2. Description of the Related Art
Conventionally, an electrically erasable programmable read-only memory (EEPROM), which electrically performs data write-in and erasure, for example, has been known as a nonvolatile semiconductor memory (R. Shirota, ‘A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend’, Nonvolatile Semiconductor Memory Workshop (NVSMW), 2000, p. 22-31). In this EEPROM, especially a NAND type, a memory cell array is configured by disposing memory cell transistors at the respective intersections of word lines in the row direction and bit lines in the column direction. A MOS transistor having a stacked gate structure configured by stacking a floating gate and a control gate, for example, is typically used as a memory cell transistor.
As presented in R. Shirota, ‘A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend’, Nonvolatile Semiconductor Memory Workshop (NVSMW), 2000, p. 22-31, a NAND-type flash memory has a structure with multiple memory cell transistors connected in series forming a NAND string, and select transistors are arranged on both sides thereof, respectively. Furthermore, a memory cell array is configured with device isolating regions arranged in parallel to device activating regions in the memory cell transistor. Typically, the gate length of each select transistor is longer than that of a memory cell transistor, preventing deterioration in transistor cutoff characteristics due to a short channel effect. In addition, the select transistor is typically configured with an enhancement-type MOS transistor.
A structure of a nonvolatile semiconductor memory, which uses a memory cell transistor configured from two types of transistors such as a memory cell transistor and a select transistor and has differing gate oxide thicknesses for the memory transistor unit and the select transistor unit, respectively, has already been disclosed (Japanese Laid-open Patent Application No. 2000-269361).
In addition, a structure with the film thickness of the gate oxide of the gate electrode of a select MOS transistor differing from that of a peripheral circuit MOS transistor has already been disclosed (Japanese Laid-open Patent Application No. Hei 04-165670).
Furthermore, a structure of a flash memory having the peripheral transistors being formed through a salicide process and the memory cell transistor region being formed with the salicide-covered control gates and the not-covered salicide diffused layers in a memory cell unit, and a fabrication method thereof has been proposed (Japanese Laid-open Patent Application No. 2003-60092).
With a conventional nonvolatile semiconductor memory such as a flash EEPROM and the like, a high voltage circuit region is necessary for supplying a high-voltage pulse such as a write-in voltage, an intermediate voltage or an erasure voltage to a memory cell array region. There are also conventional low voltage circuit regions that must operate at a low voltage and high speed.
However, usage of a transistor in the low voltage circuit region capable of operating with a higher driving capability at a higher speed is advantageous. In the low voltage circuit region of a flash EEPROM, which is operable at a low power supply voltage, ensuring the transistor driving capability is a particular objective. As the large scale integrating capacity of a memory cell array increases, improving write-in and read-out speed by decreasing the resistance on word lines in a memory cell transistor region becomes a more significant issue.
A transistor with an improved transistor driving capability and higher speed performance is necessary in the low voltage circuit regions. With the high capacity memory cell array, formation of a metallic salicide film on a gate or a diffused layer is one method for decreasing the resistance on word lines in the memory cell transistor region so as to improve write-in and read-out speed.
However, with the nonvolatile semiconductor memory such as a flash EEPROM, when forming a metallic salicide film on the gates or diffused layers of all circuit regions, as with CMOS logic circuits, avoiding an increase in junction leaks or degradation in junction withstand voltage or surface withstand voltage is an objective with the transistors in the high voltage circuit regions, which are arranged for generating a high voltage of 15V or higher such as a write-in voltage Vpgm or erasure voltage Verase.
Especially with a NAND-type memory cell transistor, a problem of junction leaks or junction withstand voltage becomes evident since it requires a higher voltage than an AND or NOR type.